1. Field of the Invention
The present invention relates to the field of digital testers. More specifically, the present invention relates to digital testers that perform high speed functional testing of an integrated circuit or a system.
2. Background Information
Conventional digital testers functionally test high speed integrated circuits by inputting a sequence of test vectors into the integrated circuit, performing a series of test operations on the integrated circuit, and then evaluating a sequence of output test vectors to determine if the integrated circuit is generating the correct data for each test operation. Conventional digital testers include testers such as integrated circuit testers, system testers, logic analyzers and circuit emulators. However, as integrated circuits are designed to operate at faster speeds, the conventional digital testers do not have the capability to capture high frequency data streams, also known as output test vectors, from the integrated circuits operating under real time test conditions. As such, the functionality of an integrated circuit is tested at frequencies slower than the actual operating frequency of the device when operating under normal conditions and the real time performance of an integrated circuit is not tested. Conventional digital testers such as the Cadence LT-1001, the Synopsis LM-1400, the Synopsis MS-3400 and the Phillips PM-3580 are not able to functionally test an integrated circuit operating at a speed faster than 100 Megahertz (MHz). However, the present invention has the capability to capture output test vectors having a frequency beyond 100 MHz and thus the ability to perform real time functional testing on integrated circuits operating over an increased range of frequencies. The present invention has the capability to capture data streams up to 1 Gigahertz (GHz).
Furthermore, the conventional digital testers have a complicated control and clock distribution system that is associated with the interleaving of memory devices used for storing the input and output test vectors. FIG. 1 illustrates a device under test 160 that is coupled to a conventional digital tester 100. The conventional digital tester 100 stores the output test vectors in a memory device 120 such as a dynamic random access memory (DRAM) or a static random access memory (SRAM). In order to improve the access time to and from the memory device 120, several banks of memory are interleaved requiring a complicated control logic and clock distribution scheme.
The following example illustrates some of the complexities involved in designing a clock distribution scheme for an interleaved memory device. The clock distribution scheme can be designed to provide a single high frequency (F) clock or as N different clocks of frequency F/N, where N represents the number of banks of the interleaved memory devices. If a single high frequency clock is used, the transmission line effect on clock line 140 will be severe. If multiple clocks of lower frequencies are used, additional circuits for stabilizing the relative skew of the various clock lines must be provided. In both of the cases mentioned above, the distribution of the clock throughout all of the interleaved memory devices is more complex than in the present invention. The simplicity of the control and clock distribution scheme of the present invention will be apparent from the detailed description below.
Another drawback with many of the conventional digital testers is that they require an external clock signal that is centered at the middle of the data period. Thus, in addition to receiving the output test vectors over data line 130, the tester 110 requires an external clock signal over clock line 140. This drawback precludes the conventional digital tester from testing serial data communication chips that do not generate an external clock signal. The present invention eliminates the need for an external clock signal from the device under test, and therefore has the ability to test asynchronous outputs of a device and is extremely useful in testing data communication chips and systems.